1. Field of the Invention
The present invention relates to a III-V compound group semiconductor device, and more particularly to a III-V compound group semiconductor device characterized by a wiring, a resistance, and an ohmic electrode built into a field effect transistor (FET).
2. Related Background Art
An alloyed ohmic contact method has been known as one of methods for forming an ohmic contact of an FET on a semiconductor substrate. In this method, a metal as a base and a metal as dopant are deposited on the semiconductor substrate and they are alloyed by a thermal process to form the ohmic contact. Ag or In is used as the base electrode, Si, Ge or Sn frequently is used for an n-type dopant, and Zn, Be or Mg frequently is used for a p-type dopant. Among others, a two-layered ohmic contact having an AuGe layer formed on a GaAs substrate and having a Ni layer formed thereon is frequently used.
FIG. 1 shows an FET having an ohmic electrode structure formed by the prior art method. A pair of ohmic electrodes 4a and 4b for a source and a drain are formed on the opposite sides of a gate electrode 20 formed on an n-type GaAs substrate 1, and a pair of ohmic electrode wirings 60a and 60b are formed to cover the ohmic electrodes. The ohmic electrodes 4a and 4b are of the AuGe/Ni structure described above.
FIGS. 2A-2F and FIG. 3 show the AuGe/Ni two-layered ohmic electrode and a method for forming the same. The forming method is first explained. An interlayer insulation film 2 is vacuum-deposited on the GaAs substrate 1 (step 201 in FIG. 3, and FIG. 2A). A photoresist material is applied on the interlayer insulation film 2 to form a resist pattern 6 having an opening at an ohmic electrode formation area (step 202 in FIG. 3, and in FIG. 2B). Then, the interlayer insulation film 2 is partially etched to form an electrode pattern (step 203 in FIG. 3, and FIG. 2C). An AuGe layer 7 is vacuum-deposited on the GaAs substrate 1 having the electrode pattern formed thereon. An Ni layer 8 is further vacuum-deposited on the AuGe layer 7 (step 204 in FIG. 3, and FIG. 2D). Then, unnecessary metal is removed by a lift-off method (step 205 in FIG. 3, and FIG. 2E). The AuGe layer 7 and the Ni layer 8 formed in the above steps are heated to an alloying temperature to form an ohmic electrode made of AuGe/Ni alloy 3 (step 206 in FIG. 3, and FIG. 2F).
Besides the ohmic electrode formed by the above method, an ohmic electrode formed by a second prior art method is known. In this method, an AuGe/Au ohmic electrode is formed on the n-type GaAs substrate 1.
An ohmic electrode formed by a third prior art method is also known. In this method, a refractory metal alloy or silicide is sandwiched between an AuGe layer and an Au layer such as an AuGe/TiW/Au structure or an AuGe/WSi/Au structure on the n-type GaAs substrate 1. (See Japanese Laid-Open Patent Publication No. 58-135668).
In the prior art ohmic electrode, a resistance of the electrode can be reduced by applying Au to the surface thereof. However, in the ohmic electrode by the first prior art method described above, when the Au layer is formed directly on the Ni layer and heated to the alloying temperature, a so-called ball-up phenomenon may occur. The ball-up means a phenomenon in which irregular alloying proceeds. The flatness of the electrode is lost, and in a long range, Au reacts with GaAs to deteriorate the reliability. In order to prevent the ball-up, metal may be inserted between the Ni layer and the Au layer. The formation of the metal must be done by a sputtering method because it is difficult to raise the temperature to the melting point by the vacuum deposition method. However, when the sputtering method is used, the metal is also formed on the side wall of the aperture (ohmic electrode formation area) of the photoresist. This makes the removal of the metal by the lift-off method impossible. Accordingly, in the prior art electrode formation method, the Au thin film cannot be applied to the surface.
In the above ohmic electrode structure, a measure to reduce the resistance in a post process is required because the resistance of the ohmic electrode is raised. To this end, ohmic electrode wirings 60a and 60b cover the entire surfaces of the ohmic electrodes 4a and 4b as shown in FIG. 1. As a result, other wirings cannot be formed to cross the ohmic electrodes 4a and 4b, and this causes the reduction of an integration density of the semiconductor device.
In the ohmic electrode structure formed by the second prior art method, the resistance of the ohmic electrode is maintained low but the upper Au layer and the Ga of the substrate react and it raises a problem with respect to the reliability of the semiconductor device.
In the ohmic electrode structure formed by the third prior art method, the resistance of the ohmic electrode is maintained low but it is difficult to reduce the resistance of the ohmic contact area.
The wiring in the prior art semiconductor device is now discussed. The wiring by Au (Au wiring layer) is usually not provided directly on the underlying insulation film, but a Ti layer or a Ti/Pt structure layer (which is a lamination of a Ti layer and a Pt layer) is frequently formed between the Au wiring layer and the underlying insulation film. The Ti layer enhances the coupling of the underlying insulation film and the Au wiring layer, and the Pt layer functions as a barrier metal to prevent the mutual diffusion of Ti and Au. Accordingly, the Pt layer is provided on the Ti layer or it is not provided, depending on the application and the life of the semiconductor device.
The above structure is described in "1991 IEEE International Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS" p. 152-153, P. 308.
However, Au and Ti react at a temperature of higher than 300.degree. C. to form an alloy layer having a high resistance. Accordingly, the Ti/Au wiring structure having the lamination of the Ti layer and the Au wiring layer has a short lifetime in view of the reliability of the semiconductor device. When a multi-layer wiring is formed by using a Ti/Pt/Au structure having a lamination of a Ti layer, a Pt layer and an Au layer, the Au (gold) 114 of a first layer wiring 110 and the Ti (titanium) 123 of a second layer wiring 120 contact in a through-hole 130 by which the first layer wiring 110 and the second layer wiring 120 are connected, as shown in FIG. 4. As a result, the mutual diffusion occurs in that area and the reliability is deteriorated.
The film resistance in the prior art semiconductor device is now discussed with reference to FIGS. 5A-5D.
FIGS. 5A-5D show steps of a prior art method for forming a high resistance film and a peripheral wiring on an insulation film on the surface of the substrate.
A resistor metal Ni-Cr-Si layer 222 is formed on an insulation film 221 deposited on the surface of the substrate. A photoresist 223 is applied on the Ni-Cr-Si layer 222, and it is patterned into a shape of a desired high resistance film (FIG. 5A). The Ni-Cr-Si layer 222 is etched by using the photoresist 223 as a mask, and an insulation film 224 is formed thereon (FIG. 5B). Contact holes 225 and 226 are formed in the insulation film 224 (FIG. 5C), and a metal wiring Au layer 227 is formed on the insulation film 224 and in the contact holes 225 and 226 (FIG. 5D). The Ni-Cr-Si layer 222 which is the high resistance film and the metal wiring Au layer 227 are electrically connected by the formation of the Au layer 227.
In the prior art manufacturing method described above, the resistance fluctuates because the dimension of the high resistance film is determined by the positions of the contact holes 225 and 226. Further, since margin for positioning between the high resistance film and the wiring is required, it is not suitable for high integration density.